1. Field of the Invention
The present invention is related to a false-positive detection prevention circuit for preventing false-positive detection where an abnormal signal, such as one comprising a lot of noise, or one that penetrates a transmission from an outside source, is superimposed on a multiplexed signal (an image signal, control signal or the like), and the resulting signal is detected as a normal signal, and more particularly, to a false-positive detection prevention circuit for preventing the false-positive detection of a Vertical Blanking Interval (VBI) signal.
2. Description of Related Art
When an image signal receiver like a television set displays images, an additional service incidental to image display, such as a character-multiplexed broadcast or data-multiplexed broadcast, can be provided by receiving not only image signals related to the image display, but also multiplexed signals, whereby additional signals such as characters, symbols and control signals are superimposed on the image signals.
A series of additional signals for realizing such an additional service exists in the vertical blanking interval (VBI) In the NTSC system utilized in television broadcasting in the United States and Japan, 525 scanning lines are provided in image signals, and of these 525 lines, a timing corresponding to the first 21 lines of each field is allocated for use as an interval for commencing scanning. This interval is called the VBI, and the characters, symbols, control signals and other such additional signals that exist in the VBI are called VBI signals. Typical VBI signals are VBID signals and closed-captioning signals. The waveforms of a VBID signal and closed-captioning signal are shown in FIG. 24 and FIG. 25, respectively.
The VBID signal shown in FIG. 24 is a bit array signal with a start code of “10,” and is an NRZ (non-return to zero) format signal characterized by a fixed data period in the start code and data region.
The closed captioning signal shown in FIG. 25 is a bit array with a start code of “001,” and is a signal that has a 16-bit data region. Before the start code, there is a clock run-in signal comprising pulses that are repeated a predetermined number of times at a fixed period.
An image signal receiver carries out image display and character output resulting from a multiplexed broadcast by reading the data in the VBI signal synchronized with a vertical synchronization signal and a horizontal synchronization signal in the image signal. However, a displayed image becomes distorted when the state of an airwave deteriorates, an image signal degrades due to an increase in noise, or a foreign signal enters from outside.
In particular, when noise increases in the VBI, this gives rise to such problems as the VBI signal deteriorating, and displayed characters and symbols either becoming distorted or garbled. Accordingly, control is implemented for solving problems like these by detecting either deteriorating VBI signals or unrelated signals that penetrate from outside as error signals, and not displaying the abnormal data of the data region.
Due to false detection that falsely detects an error signal as a VBI signal, a case that displays characters, symbols and so on which are not supposed to be displayed occurs. Technology development related to false-positive detection prevention is being carried out for preventing the occurrence of such cases.
FIG. 26 shows a block diagram of a conventional false-positive detection prevention circuit for preventing false-positive detections. In the conventional false-positive detection prevention circuit, slice timing set in accordance with a slice timing setting circuit 5 is used as a sampling clock for VBI signal slices, and this sampling clock determines the sampling position.
In a first method for setting slice timing, based on a horizontal synchronization signal obtained by synchronization separation from an input video signal, a slice timing setting circuit 5 sets slice timing by capturing horizontal synchronization timing and setting a constant frequency. Further, in a second method, a phase locked loop (PLL) 4 sets slice timing by frequency/phase synchronizing it to a clock run-in signal based on a clock run-in time pulse output by a synchronization separation circuit 3. Furthermore, the PLL 4 is only used when a clock run-in signal is included in a signal.
In the meantime, noise is removed from the input video signal by an LPF (low pass filter) 1, and a binary determination value is output from a comparator 2 based on a slice level set from outside.
A sampling hold circuit 6 receives a binary determination value and a signal for setting slice timing, and outputs slice data, which is a VBI signal sliced in accordance with a slice level.
A start code detection circuit 10 receives slice data from the sampling hold circuit 6. The start code detection circuit 10 carries out sampling for the received slice data in accordance with slice timing, determines whether or not a slice value at a sampling position coincides with the value of the start code (framing code), and outputs the results. When the start code detection circuit 10 determines that a slice value does not coincide with the start code value, it outputs an error signal. When an error signal is output from the start code detection circuit 10, control is implemented such that a display corresponding to the input video signal is not carried out, thus preventing a false-positive detection.
However, such conventional false-positive detection prevention method is not effective since there is a strong likelihood that a false-positive detection will occur when evaluating a start code based solely on a slice determination for a VBI signal at a sampling position.
For example, even in a case where a VBI signal is not superimposed on the video signal and a random signal is input, when a waveform that coincides with a start code is randomly detected at a sampling position due to the effects of noise, a determination is made that a VBI signal exists, causing a malfunction. In other words, when an abnormal pulse where a plurality of data change-points exist is inputted between one sampling position and the next sampling position in the VBI, it is mistakenly determined as a normal pulse signal since this determination is made based solely on the interval of a VBI-signal-slicing sampling clock and as such is not capable of detecting these change-points.
FIG. 27A shows the results of implementing false-positive detection prevention in a conventional false-positive detection prevention circuit. FIG. 27A shows a case where a VBID signal has been input as a VBI signal. As shown in the figure, a binary determination value is output in accordance with a set slice level. Sampling positions are determined in accordance with slice timing of a horizontal synchronization signal. Since the sampling interval is the same as the data period, the slice determination result of the slice data is favorable in that it shows the slice value of a VBI signal.
FIG. 27B shows a case where a VBI signal, which comprises a lot of noise and should be determined to be an error signal, is input. Similar to the case in FIG. 27A, binary determination values and sampling positions are determined, but change-points in binary determination values exist between a certain sampling position and an adjacent sampling position. In the conventional method, since a determination of “1” or “0” is only carried out for a binary determination value at either the rising edge or falling edge of the sampling clock, the above-mentioned change-points cannot be detected and the slice determination result becomes the same as the case in FIG. 27A. Thus, the VBI signal is not determined to be an error signal, and false-positive detection occurs. Moreover, if start code coincidence alone is evaluated as in the conventional method, the evaluation area will become even narrower, and the ratio of false-positive detections will become larger.
Techniques related to false-positive detection prevention have been disclosed for methods other than those described hereinabove, and typical such techniques will be explained.
In Japanese Unexamined Patent Publication No. 2000-197016, a data extraction circuit for reproducing character data such as closed captions and text data generates a horizontal synchronization signal-synchronized clock signal for data extraction such that character data can be stably reproduced despite picture signal deterioration and frequency fluctuations. Then, the number of cycle of a clock run-in signal is detected on the basis of the data extraction clock signal, and for start bit detection, a determination is made as to whether or not a VBI signal should be detected by comparing a VBI signal with a reference value.
However, in detecting only the number of cycles of a run-in clock, even when a signal that does not coincide with the period of a detected VBI signal is input, when the cycle number is the same as the cycle number of a detected VBI signal, it may be determined that a clock run-in signal exists and there is a VBI signal to be detected. Further, with regard to start bit detection, the problem is that since comparison is made with a reference value, a false signal with a degree of coincidence approaching the threshold value is detected as a false positive.
Japanese Unexamined Patent Publication No. 11-32308 discloses a conventional method where an abnormal determination is made by comparing a horizontal synchronization signal with an HD signal, the period of which is more orderly than that of the horizontal synchronization signal in order to prevent erroneous data from being output as extraction data when distorted multiplexed signals are input.
However, when the horizontal synchronization signal is normal, and a signal other than a detected VBI signal is input, there is a high likelihood of a false-positive detection occurring since an abnormal determination is not made.
In all of the techniques described hereinabove, a timing, value or signal constituting a reference is set for preventing false-positive detection, and then an evaluation for determining whether or not there is an error is carried out by comparing the set reference timing, value or signal against an input signal timing, value or signal. However, due to the fact that a VBI signal that intrinsically would trigger a false-positive detection resembles the timing, value or signal to be compared in the comparison-based evaluation method, there is an increased likelihood of a determination being made that indicates there is no error, resulting in a higher ratio of false-positive detections.